The present invention is related to logic array integrated circuit structures and, more specifically, to BiCMOS logic array integrated circuit structures.
A logic array is an integrated circuit device having an array of partially connected semiconductor devices, most of which are transistors. The integrated circuit is completed by the specification of the layout of the conducting layers, typically two, which interconnect the semiconductor devices. The layout of the conducting layers adapt the generic logic array to the user's specific needs.
Associated with the logic array is a macrocell library which is a compilation of layout patterns for the conducting layers to implement commonly used logic function blocks, such as NAND, NOR, flip-flop, counters and the like, with interconnected semiconductor devices. A user adapts the array by specifying the logic function blocks and their interconnection. The resulting integrated circuit is particularly designed for the user's requirements in this manner.
A constraint for logic arrays is that conducting lines formed by layout patterns must be conserved. Once an area in a conducting metal layer is delineated and used for connecting points within a macrocell, for instance, it is not also available for connecting macrocells to each other.
With this constraint logic arrays are ideally implemented for maximum flexibility and compactness. The logic array should not only be able to compactly realize as many logic function blocks as possible, but also the logic array should be such that a macrocell may be positioned in as many locations in the array as possible. This allows for the different macrocells of the desired integrated circuit to be located closely together for a compact design, a desirable goal in integrated circuits, with the conducting layers between the macrocells available to form the interconnecting conducting lines.
For example, one such flexible and compact logic array design is described in the present assignee's U.S. Pat. No. 4,884,118, entitled "Double Metal HCMOS Compacted Array," issued to A.C. Hui et al. on Nov. 28, 1989. That patent teaches a flexible and high density logic array in CMOS (Complementary Metal Oxide Semiconductor) technology. However, heretofore logic arrays in BiCMOS technology have not been entirely satisfactory in terms of flexibility and compactness. In BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) technology bipolar technology is combined with that of CMOS. In a BiCMOS integrated circuit, the higher-speed bipolar transistors are located at the suitable locations to use the speed and drive capabilities inherent in bipolar transistors. The CMOS transistors are used wherever higher packing densities and lower power consumption of CMOS circuits are suitable.
Thus the present invention is directed toward a BiCMOS logic array which is much more compact and flexible than BiCMOS logic arrays heretofore.